1. Field of the Invention
The present invention relates to a memory compiler and, more particularly, circuit and method to build a memory compiler based on pre-built memory templates of maximum capacities with array size reduction and component subtraction.
2. Description of the Related Art
Memory compiler is a tool to generate memories with various configurations, such as different capacities, different I/O counts, different aspect ratios, etc. by software automation. The conventional method to build a compiler is based on an additive approach or tiling, which means all basic components of a memory are pre-built and then tiled together seamlessly like tiling on the kitchen floor by running a software.
Compilers to generate datapath, such as adders or multipliers, or to generate register files is a very simple example of tiling. As an example to generate an 8-bit, 16-bit, 32-bit, or 64-bit adder, each bit cell is pre-designed and pre-layouted. The cells of carry look-ahead or carry select for every 4 bits can also be pre-designed and pre-layouted. Then a simple layout script or a software script tiles the bit slices together with carry look-ahead or carry select circuit between 4-bit cells to generate the required adder. Register file is another simple example for tiling. The bit cells, X-decoders, and column sense amplifiers can be put together to generate the required register file with arbitrary capacities and configurations.
ROM or SRAM compilers are another two common types of memory compilers that need a general purpose software rather than simple scripts to generate. A ROM or SRAM has memory bit cells, X-decoders, Y-decoders, X- and Y-address buffers, X- and Y-pre-decoders, bitline pull-ups, Y-select pass gates, sense amplifiers, output buffers, and control logic, etc. Those components need more sophisticated software to tile various components together to generate various configurations, such as capacities, I/Os, aspect ratios, on different technologies, etc.
FIG. 1 shows a portion of a typical ROM/SRAM compiler 100 based on tiling according to a prior art. The memory bit cell 105 is built and organized as an n×m two-dimensional memory array 110 by tiling all bit cells together. Then, n X-decoders 115 are tiled and butted to the left of the memory array 110 with the height of the X-decoders 115 fitted into the height of the bit cells 105. Similarly, m Y-decoders 120 are tiled and butted to the bottom of the memory array 110 with the width of the Y-decoders fitted into the width of the bit cell 105. The X- and Y-decoders are called tight-pitch cells that need to fit into the pitches of the bit cells 105, otherwise the area utilization would be very poor. S columns are multiplexed into one I/O so that one sense amplifier 125 has a width to match the width of s bit cells 105. If there are t sense amplifiers 125 in the memory 100 and one sense amplifier fitting into the width of s cells, then the total number of column in the memory 100 is m=s*t. Output buffers 130 are tiled to the bottom of the sense amplifier 125, one for one. All X- and Y-addresses need to be properly buffered and then pre-decoded to generate the required X- and Y-decoder signals. The X-address buffers 135 and X-pre-decoders 140 are built and generally fitted into the left-lower corner in the floor plan. So do the Y-address buffers 145 and Y-pre-decoders 150. Then the read/write control logic 195 is built to fit into the left over space in the left-lower corner of the memory macro 100. All components are tiled with perfect matches in the boundaries to prevent wasting valuable silicon real estate. Finally, a power/ground ring (not shown in FIG. 1) is built around the whole memory macro 100 to complete the memory compiled.
The above compiler method is only good for a simple memory such as ROM or SRAM. For a DRAM or flash memory, the components are much more and complicated. For example, flash memory tends to need high voltage generators, reference voltages, tighter pitches but with high-voltage devices in the X- and Y-decoders to fit. As a result, they tend to build manually, rather than generated by software automatically.
Building memories with different configurations manually requires lots of time, efforts, and financial resources to do. Moreover, it would be subject to human errors, that may carry great financial and legal liability. Accordingly, there is a need for building a general-purpose memory compiler for those memories that are more complicated than either ROM or SRAM to save costs.